The Idea Technology
"We have to reinvent computing, and get away from the fundamental premises we inherited from traditional compilers." - Burton Smith, Technical Fellow, Microsoft
Gedae's key innovation is the shift of complexity typical found in a software or hardware stack to compilation.
Gedae's well developed technology automatically creates highly efficient applications for multi-core, multiprocessor and complex memory architectures. The solution abandons the traditional software stack that is built on compilers for single cores and provides a new solution better suited to modern and future multi-cores.
Gedae’s technology consists of four major components (see figure 1): a language, an architectural modeling language, an OS and a compiler. These four components were designed together as interrelated parts in a single, all-in-one solution.
Gedae’s Idea© language combines data-flow language abstractions, high level algebra and math similar to Matlab, and control similar to UML (e.g. state machines).
The compiler is the confluence of the complexity of Gedae. It is beyond the scope of this white paper to describe how the compiler works. The compiler deals with many types of issues and performs many optimizations. The compiler’s key objectives are efficiency and scalability. Not just efficiency sufficient enough for improvement when adding cores, but close to the metal efficiency equivalent to what a highly skilled hand coder would produce with ample time to tweak and optimize. The compiler also guarantees portability, as enabled by the architectural modeling language described above, and correctness, guaranteeing thread safety.
Gedae’s OS is co-designed with the compiler. The OS is simple and handles the runtime activities that cannot be built into the code. The OS can be simple and small because the compiler builds traditional OS functionality directly into the application to the greatest extent possible.
Gedae's Architectural Modeling Language is used to create a hardware model of the target architecture. The hardware model describes the details of the target hardware with information the compiler needs to construct the software.
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