The Gedae Idea Compiler
The compiler is the confluence of the complexity of Gedae. It is beyond the scope of this discussion to describe how the compiler works. The compiler deals with many types of issues and performs many optimizations. The compiler’s key objectives are efficiency and scalability. Not just efficiency sufficient enough for improvement when adding cores, but close to the metal efficiency equivalent to what a highly skilled hand coder would produce with ample time to tweak and optimize. The compiler also guarantees portability, as enabled by the architectural modeling language described above, and correctness, guaranteeing thread safety.
The developer has complete control over the implementation with the ability to specify every detail of the implementation. Generally the developer only changes the default specification for distribution and interconnects particulars. Part of the continuing evolution of Gedae is a component that optimizes the implementation specifications based on the application and architecture. The manual optimization as it is done now is a minor portion of the development effort. It is a true specification – e.g. put this data on this processor, put that function on another processor, use a socket transfer for this data (versus DMA for example), and so on.
The following is a list of the most important efficiencies and issues:
- All behavior is fully optimized for the application and the target
- Efficient context switch times
- Eliminate deadlock and race conditions
- Optimal plan memory use at compile time
- No unnecessary dynamic allocation
- Preplanned memory management minimizes data and code footprint
- Optimize memory alignment
- Optimal use of IPC to maximize concurrency
- Automatic multi-buffering for efficient DMA
- Efficient data re-org
- Automatic optimal placement of concurrency controls
- Automatic implementation of data and code cache management
- Optimal use of cache and memory hierarchy
- Optimize code and data locality
- Optimize granularity of processing for:
- Optimal use of memory hierarchy
- High CPU performance
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